View 8242AH_8538503.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

november 1994 order number: 210393-008 upi-41ah/42ah universal peripheral interface 8-bit slave microcontroller y upi-41: 6 mhz; upi-42: 12.5 mhz y pin, software and architecturally compatible with all upi-41 and upi-42 products y 8-bit cpu plus rom/otp eprom, ram, i/o, timer/counter and clock in a single package y 2048 x 8 rom/otp, 25 6 x 8 ram on upi-42, 102 4 x 8 rom/otp, 128 x 8 ram on upi-41, 8-bit timer/counter, 18 programmable i/o pins y one 8-bit status and two data registers for asynchronous slave-to- master interface y dma, interrupt, or polled operation supported y fully compatible with all intel and most other microprocessor families y interchangeable rom and otp eprom versions y expandable i/o y sync mode available y over 90 instructions: 70% single byte y available in express e standard temperature range y int e ligent programming algorithm e fast otp programming y available in 40-lead plastic and 44- lead plastic leaded chip carrier packages (see packaging spec., order y 240800-001) package type p and n the intel upi-41ah and upi-42ah are general-purpose universal peripheral interfaces that allow the designer to develop customized solutions for peripheral device control. they are essentially ``slave'' microcontrollers, or microcontrollers with a slave interface included on the chip. interface registers are included to enable the upi device to function as a slave peripheral controller in the mcs modules and iapx family, as well as other 8-, 16-, and 32-bit systems. to allow full user flexibility, the program memory is available in rom and one-time programmable eprom (otp). all upi-41ah and upi-42ah devices are fully pin compatible for easy transition from prototype to production level designs. 210393 2 figure 1. dip pin configuration 210393 3 figure 2. plcc pin configuration
upi-41ah/42ah 210393 1 figure 3. block diagram upi product matrix upi rom otp ram programming device eprom voltage 8042ah 2k e 256 e 8242AH 2k e 256 e 8742ah e 2k 256 12.5v 8041ah 1k e 128 e 8741ah e 1k 128 12.5v the intel 8242 as shown in the upi-42 product matrix, the upi-42 will be offered as a pre-programmed 8042 with sev- eral software vendors' keyboard controller firmware. the current list of available 8242 versions include keyboard controller firmware from both phoenix technologies ltd., ibm, and award software inc. the 8242 is programmed with phoenix technologies ltd. keyboard controller firmware for at-compatible systems. this keyboard controller is fully compatible with all at-compatible operating systems and appli- cations. the 8242pc also contains phoenix tech- nologies ltd. firmware. this keyboard controller provides support for at, ps/2 and most eisa plat- forms as well as ps/2-style mouse support for either at or ps/2 platforms. the intel 8242bb is programmed with ibm's key- board controller firmware. the 8242bb provides an off the shelf keyboard and auxiliary device controller for at, ps/2, eisa, and pci architectures. the 8242wa contains award software inc. firm- ware. this device provides at at-compatible key- board controller for use in ibm pc at compatible computers. the 8242wb contains a version of award software inc. firmware that provides ps/2 style mouse support in addition to the standard fea- tures of the 8242wa. * contact factory for current code revision available in all versions of the 8242 product lines. 2
upi-41ah/42ah table 1. pin description dip plcc symbol pin pin type name and function no. no. test 0, 1 2 i test inputs: input pins which can be directly tested using conditional branch instructions. test 1 39 43 frequency reference: test 1 (t 1 ) also functions as the event timer input (under software control). test 0 (t 0 ) is used during prom programming and rom/eprom verification. it is also used during sync mode to reset the instruction state to s1 and synchronize the internal clock to ph1. see the sync mode section. xtal 1, 2 3 i inputs: inputs for a crystal, lc or an external timing signal to determine the internal oscillator frequency. xtal 2 3 4 reset 45i reset: input used to reset status flip-flops and to set the program counter to zero. reset is also used during eprom programming and verification. ss 56i single step: single step input used in conjunction with the sync output to step the program through each instruction (eprom). this should be tied to a 5v when not used. this pin is also used to put the device in sync mode by applying 12.5v to it. cs 67i chip select: chip select input used to select one upi microcomputer out of several connected to a common data bus. ea 7 8 i external access: external access input which allows emulation, testing and rom/eprom verification. this pin should be tied low if unused. rd 89i read: i/o read input which enables the master cpu to read data and status words from the output data bus buffer or status register. a 0 910i command/data select: address input used by the master processor to indicate whether byte transfer is data (a 0 e 0, f1 is reset) or command (a 0 e 1, f1 is set). a 0 e 0 during program and verify operations. wr 10 11 i write: i/o write input which enables the master cpu to write data and command words to the upi input data bus buffer. sync 11 13 o output clock: output signal which occurs once per upi instruction cycle. sync can be used as a strobe for external circuitry; it is also used to synchronize single step operation. d 0 d 7 (bus) 1219 1421 i/o data bus: three-state, bidirectional data bus buffer lines used to interface the upi microcomputer to an 8-bit master system data bus. p 10 p 17 2734 3033 i/o port 1: 8-bit, port 1 quasi-bidirectional i/o lines. p 10 p 17 access the signature row and security bit. 3538 p 20 p 27 2124 2427 i/o port 2: 8-bit, port 2 quasi-bidirectional i/o lines. the lower 4 bits (p 20 p 23 ) interface directly to the 8243 i/o expander device and contain address and data information during 3538 3942 port 4 7 access. the upper 4 bits (p 24 p 27 ) can be programmed to provide interrupt request and dma handshake capability. software control can configure p 24 as output buffer full (obf) interrupt, p 25 as input buffer full (ibf ) interrupt, p 26 as dma request (drq), and p 27 as dma acknowledge (dack ). prog 25 28 i/o program: multifunction pin used as the program pulse input during prom programming. during i/o expander access the prog pin acts as an address/data strobe to the 8243. this pin should be tied high if unused. v cc 40 44 power: a 5v main power supply pin. v dd 26 29 power: a 5v during normal operation. a 12.5v during programming operation. low power standby supply pin. v ss 20 22 ground: circuit ground potential. 3
upi-41ah/42ah upi-41ah and upi-42ah features 1. two data bus buffers, one for input and one for output. this allows a much cleaner master/slave protocol. 210393 4 2. 8 bits of status st 7 st 6 st 5 st 4 f 1 f 0 ibf obf d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 st 4 st 7 are user definable status bits. these bits are defined by the ``mov sts, a'' single byte, single cycle instruction. bits 4 7 of the acccumu- lator are moved to bits 4 7 of the status register. bits 0 3 of the status register are not affected. mov sts, a op code: 90h 1 001000 0 d 7 d 0 3. rd and wr are edge triggered. ibf, obf, f 1 and int change internally after the trailing edge of rd or wr . 210393 6 during the time that the host cpu is reading the status register, the upi is prevented from updat- ing this register or is `locked out.' 4. p 24 and p 25 are port pins or buffer flag pins which can be used to interrupt a master proces- sor. these pins default to port pins on reset. if the ``en flags'' instruction has been execut- ed, p 24 becomes the obf (output buffer full) pin. a ``1'' written to p 24 enables the obf pin (the pin outputs the obf status bit). a ``0'' written to p 24 disables the obf pin (the pin remains low). this pin can be used to indicate that valid data is avail- able from the upi (in output data bus buffer). if ``en flags'' has been executed, p 25 becomes the ibf (input buffer full) pin. a ``1'' written to p 25 enables the ibf pin (the pin outputs the inverse of the ibf status bit. a ``0'' written to p 25 disables the ibf pin (the pin remains low). this pin can be used to indicate that the upi is ready for data. 210393 5 data bus buffer interrupt capability en flags op code: 0f5h 1 111010 1 d 7 d 0 4
upi-41ah/42ah 5. p 26 and p 27 are port pins or dma handshake pins for use with a dma controller. these pins default to port pins on reset. if the ``en dma'' instruction has been executed, p 26 becomes the drq (dma request) pin. a ``1'' written to p 26 causes a dma request (drq is acti- vated). drq is deactivated by dack # rd, dack # wr, or execution of the ``en dma'' in- struction. if ``en dma'' has been executed, p 27 becomes the dack (dma acknowledge) pin. this pin acts as a chip select input for the data bus buffer reg- isters during dma transfers. 210393 7 dma handshake capability en dma op code: 0e5h 1 110010 1 d 7 d 0 6. when ea is enabled on the upi, the program counter is placed on port 1 and the lower three bits of port 2 (msb e p 22 , lsb e p 10 ). on the upi this information is multiplexed with port data (see port timing diagrams at end of this data sheet). 7. the 8741ah and 8742ah support the int e ligent programming algorithm. (see the programming section.) 210393 8 figure 5. 8088-upi-41ah/42ah interface 210393 10 figure 6. 8048h-upi-41/42 interface 210393 9 figure 7. upi-41/42-8243 keyboard scanner applications 210393 30 figure 4. upi-41ah/42ah keyboard controller 5
upi-41ah/42ah 210393 11 figure 8. upi-41ah/42ah 80-column matrix printer interface programming and verifying the 8741ah and 8742ah otp eprom programming verification in brief, the programming process consists of: acti- vating the program mode, applying an address, latching the address, applying data, and applying a programming pulse. each word is programmed com- pletely before moving on to the next and is followed by a verification step. the following is a list of the pins used for programming and a description of their functions: pin function xtal 1 2 clock inputs reset initialization and address latching test 0 selection of program or verify mode ea activation of program/verify signature row/security bit modes bus address and data input data output during verify p 2022 address input v dd programming power supply prog program pulse input warning an attempt to program a missocketed 8741ah or 8742ah will result in severe damage to the part. an indication of a properly socketed part is the appearance of the sync clock output. the lack of this clock may be used to disable the programmer. the program/verify sequence is: 1. cs e 5v, v cc e 5v, v dd e 5v, reset e 0v, a 0 e 0v, test 0 e 5v, clock applied or internal oscillator operating, bus floating, prog e 5v. 2. insert 8741ah or 8742ah in programming socket 3. test 0 e 0v (select program mode) 4. ea e 12.5v (active program mode) 5. v cc e 6v (programming supply) 6. v dd e 12.5v (programming power) 7. address applied to bus and p 2022 8. reset e 5v (latch address) 9. data applied to bus 10. prog e 5v followed by one 1 ms pulse to 0v 11.test 0 e 5v (verify mode) 12. read and verify data on bus 13. test 0 e 0v 14. apply overprogram pulse 15. reset e 0v and repeat from step 6 16. programmer should be at conditions of step 1 when 8741ah or 8742ah is removed from socket please follow the int e ligent programming flow chart for proper programming procedure. int e ligent programming algorithm the int e ligent programming algorithm rapidly pro- grams intel 8741ah/8742ah eproms using an effi- cient and reliable method particularly suited to the production programming environment. typical pro- gramming time for individual devices is on the order of 10 seconds. programming reliability is also en- sured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed. a flowchart of the 8741ah/8742ah int e ligent programming algo- rithm is shown in figure 9. the int e ligent programming algorithm utilizes two different pulse types: initial and overprogram. the duration of the initial prog pulse(s) is one millisec- ond, which will then be followed by a longer overpro- gram pulse of length 3x msec. x is an iteration coun- ter and is equal to the number of the initial one milli- second pulses applied to a particular 8741ah/ 8742ah location, before a correct verify occurs. up to 25 one-millisecond pulses per byte are provided for before the overprogram pulse is applied. 6
upi-41ah/42ah 210393 12 figure 9. programming algorithm 7
upi-41ah/42ah the entire sequence of program pulses and byte verifications is performed at v cc e 6.0v and v dd e 12.5v. when the int e ligent programming cycle has been completed, all bytes should be compared to the original data with v cc e 5.0, v dd e 5v. verify a verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. the verify is performed with t0 e 5v, v dd e 5v, ea e 12.5v, ss e 5v, prog e 5v, a0 e 0v, and cs e 5v. security bit the security bit is a single eprom cell outside the eprom array. the user can program this bit with the appropriate access code and the normal program- ming procedure, to inhibit any external access to the eprom contents. thus the user's resident program is protected. there is no direct external access to this bit. however, the security byte in the signature row has the same address and can be used to check indirectly whether the security bit has been programmed or not. the security bit has no effect on the signature mode, so the security byte can always be examined. security bit programming/ verification programming a. read the security byte of the signature mode. make sure it is 00h. b. apply access code to appropriate inputs to put the device into security mode. c. apply high voltage to ea and v dd pins. d. follow the programming procedure as per the int e ligent programming algorithm with known data on the databus. not only the security bit, but also the security byte of the signature row is pro- grammed. e. verify that the security byte of the signature mode contains the same data as appeared on the data bus. (if db0 db7 e high, the security byte will contain ffh.) f. read two consecutive known bytes from the eprom array and verify that the wrong data are retrieved in at least one verification. if the eprom can still be read, the security bit may have not been fully programmed though the se- curity byte in the signature mode has. verification since the security bit address overlaps the address of the security byte of the signature mode, it can be used to check indirectly whether the security bit has been programmed or not. therefore, the security bit verification is a mere read operation of the security byte of the signature row (0ffh e security bit pro- grammed; 00h e security bit unprogrammed). note that during the security bit programming, the reading of the security byte does not necessarily indicate that the security bit has been successfully pro- grammed. thus, it is recommended that two consec- utive known bytes in the eprom array be read and the wrong data should be read at least once, be- cause it is highly improbable that random data coin- cides with the correct ones twice. 8
upi-41ah/42ah signature mode the upi-41ah/42ah has an additional 32 bytes of eprom available for intel and user signatures and miscellaneous purposes. the 32 bytes are parti- tioned as follows: a. test code/checksume this can accommodate up to 25 bytes of code for testing the internal nodes that are not testable by executing from the external memory. the test code/checksum is present on roms, and otps. b. intel signature ethis allows the programmer to read from the upi-41ah/42ah the manufacturer of the device and the exact product name. it fa- cilitates automatic device identification and will be present in the rom and otp versions. loca- tion 10h contains the manufacturer code. for in- tel, it is 89h. location 11h contains the device code. the code is 43h and 42h for the 8042ah and otp 8742ah, and 41h and 40h for the 8041ah and otp 8741ah, respectively. the code is 44h for any device with the security bit set by intel. c. user signature ethe user signature memory is implemented in the eprom and consists of 2 bytes for the customer to program his own signa- ture code (for identification purposes and quick sorting of previously programmed materials). d. test signature ethis memory is used to store testing information such as: test data, bin num- ber, etc. (for use in quality and manufacturing control). e. security byte ethis byte is used to check whether the security bit has been programmed (see the security bit section). the signature mode can be accessed by setting p10 e 0, p11 p17 e 1, and then following the programming and/or verification procedures. the location of the various address partitions are as follows: address device no. of type bytes test code/checksum 0 0fh rom/otp 25 16h 1eh intel signature 10h 11h rom/otp 2 user signature 12h 13h otp 2 test signature 14h 15h rom/otp 2 security byte 1fh otp 1 9
upi-41ah/42ah sync mode the sync mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time. the sync mode may also be utilized by automatic test equipment (ate) for quick, easy, and efficient synchronizing between the tester and the dut (de- vice under test). sync mode is enabled when ss pin is raised to high voltage level of a 12 volts. to begin synchroniza- tion, t0 is raised to 5 volts at least four clock cycles after ss . t0 must be high for at least four x1 clock cycles to fully reset the prescaler and time state generators. t0 may then be brought down during low state of x1. two clock cycles later, with the ris- ing edge of x1, the device enters into time state 1, phase 1. ss is then brought down to 5 volts 4 clocks later after t0. reset is allowed to go high 5 tcy (75 clocks) later for normal execution of code. sync mode timing diagrams 210393 28 minimum specifications sync operation time, t sync e 3.5 xtal 1 clock cycles. reset time, t rs e 4t cy . note: the rising and falling edges of t0 should occur during low state of xtal1 clock. 10
upi-41ah/42ah access code the following table summarizes the access codes required to invoke the sync mode, signature mode, and the security bit, respectively. also, the programming and verification modes are included for comparison. control signals data bus access code modes port 2 port 1 t0 rst ss ea prog v dd v cc 0123456701201 234567 programming 0 0 1 hv 1 v ddh v cc address addr a 0 a 1 xxxxxx mode 0 1 1 hv stb v ddh v cc data in addr verification 0 0 1 hv 1 v cc v cc address addr a 0 a 1 xxxxxx mode 111hv1v cc v cc data out addr sync mode stb 0 hv 0 x v cc v cc xxxxxxxxxxxxx xxxxxx high signature prog 0 0 1 hv 1 v ddh v cc addr. (see sig mode table) 0 0 0 0 1 1 1 1 x x 1 mode 0 1 1 hv stb v ddh v cc data in 0 0 0 verify 0 0 1 hv 1 v cc v cc addr. (see sig mode table) 0 0 0 111hv1v cc v cc data out 0 0 0 security prog 0 0 1 hv 1 v ddh v cc address 0 0 0 bit/byte 0 1 1 hv stb v ddh v cc data in 0 0 0 verify 0 0 1 hv 1 v cc v cc address 0 0 0 111hv1v cc v cc data out 0 0 0 notes: 1. a 0 e 0or1;a 1 e 0or1.a 0 must e a 1 . absolute maximum ratings * ambient temperature under bias 0 cto a 70 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 0.5v to a 7v power dissipation 1.5 w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. d.c. characteristics t a e 0 cto a 70 c, v cc e v dd ea 5v g 10% symbol parameter upi-41ah/42ah units notes min max v il input low voltage (except xtal1, xtal2, reset) b 0.5 0.8 v v il1 input low voltage (xtal1, xtal2, reset) b 0.5 0.6 v v ih input high voltage (except xtal1, xtal2, reset) 2.0 v cc v v ih1 input high voltage (xtal1, reset) 3.5 v cc v v ih2 input high voltage (xtal2) 2.2 v cc v v ol output low voltage (d 0 d 7 ) 0.45 v i ol e 2.0 ma 11
upi-41ah/42ah d.c. characteristics t a e 0 cto a 70 c, v cc e v dd ea 5v g 10% (continued) symbol parameter upi-41ah/42ah units notes min max v ol1 output low voltage (p 10 p 17 ,p 20 p 27 , sync) 0.45 v i ol e 1.6 ma v ol2 output low voltage (prog) 0.45 v i ol e 1.0 ma v oh output high voltage (d 0 d 7 ) 2.4 v i oh eb 400 m a v oh1 output high voltage (all other outputs) 2.4 i oh eb 50 m a i il input leakage current (t 0 ,t 1 , rd, wr, cs, a 0 , ea) g 10 m av ss s v in s v cc i ofl output leakage current (d 0 d 7 , high z state) g 10 m av ss a 0.45 s v out s v cc i li low input load current (p 10 p 17 ,p 20 p 27 ) 0.3 ma v il e 0.8v i li1 low input load current (reset, ss) 0.2 ma v il e 0.8v i dd v dd supply current 20 ma typical e 8ma i cc a i dd total supply current 135 ma typical e 80 ma i dd standby power down supply current 20 ma typical e 8ma i ih input leakage current (p 10 p 17 ,p 20 p 27 ) 100 m av in e v cc c in input capacitance 10 pf t a e 25 c (1) c io i/o capacitance 20 pf t a e 25 c (1) note: 1. sampled, not 100% tested. d.c. characteristicseprogramming t a e 25 c g 5 c, v cc e 6v g 0.25v, v dd e 12.5v g 0.5v symbol parameter min max units v ddh v dd program voltage high level 12 13 v (1) v ddl v dd voltage low level 4.75 5.25 v v ph prog program voltage high level 2.0 5.5 v v pl prog voltage low level b 0.5 0.8 v v eah input high voltage for ea 12.0 13.0 v (2) v eal ea voltage low level b 0.5 5.25 v i dd v dd high voltage supply current 50.0 ma i ea ea high voltage supply current 1.0 ma notes: 1. voltages over 13v applied to pin v dd will permanently damage the device. 2. v eah must be applied to ea before v ddh and removed after v ddl . 3. v cc must be applied simultaneously or before v dd and must be removed simultaneously or after v dd . 12
upi-41ah/42ah a.c. characteristics t a e 0 cto a 70 c, v ss e 0v, v cc e v dd ea 5v g 10% dbb read symbol parameter min max units t ar cs, a 0 setup to rd v 0ns t ra cs, a 0 hold after rd u 0ns t rr rd pulse width 160 ns t ad cs, a 0 to data out delay 130 ns t rd rd v to data out delay 0 130 ns t df rd u to data float delay 85 ns dbb write symbol parameter min max units t aw cs, a 0 setup to wr v 0ns t wa cs, a 0 hold after wr u 0ns t ww wr pulse width 160 ns t dw data setup to wr u 130 ns t wd data hold after wr u 0ns clock symbol parameter min max units t cy (upi-41ah/42ah) cycle time 1.2 9.20 m s (1) t cyc (upi-41ah/42ah) clock period 80 613 ns t pwh clock high time 30 ns t pwl clock low time 30 ns t r clock rise time 10 ns t f clock fall time 10 ns note: 1. t cy e 15/f(xtal) a.c. characteristics dma symbol parameter min max units t acc dack to wr or rd 0 ns t cac rd or wr to dack 0 ns t acd dack to data valid dack to data valid 0 130 ns t crq rd or wr to drq cleared 110 ns (1) note: 1. c l e 150 pf. 13
upi-41ah/42ah a.c. characteristicseprogramming t a e 25 c g 5 c, v cc e 6v g 0.25v, v ddl ea 5v g 0.25v, v ddh e 12.5v g 0.5v (8741ah/8742ah only) symbol parameter min max units t aw address setup time to reset u 4t cy t wa address hold time after reset u 4t cy t dw data in setup time to prog v 4t cy t wd data in hold time after prog u 4t cy t pw initial program pulse width 0.95 1.05 ms (1) t tw test 0 setup time for program mode 4t cy t wt test 0 hold time after program mode 4t cy t do test 0 to data out delay 4t cy t ww reset pulse width to latch address 4t cy t r ,t f prog rise and fall times 0.5 100 m s t cy cpu operation cycle time 2.5 3.75 m s t re reset setup time before ea u 4t cy t opw overprogram pulse width 2.85 78.75 ms (2) t de ea high to v dd high 1t cy notes: 1. typical initial program pulse width tolerance e 1ms g 5%. 2. this variation is a function of the iteration counter value, x. 3. if test 0 is high, t do can be triggered by reset u . a.c. characteristics port 2 t a e 0 cto a 70 c, v cc ea 5v g 10% symbol parameter f(t cy ) (3) min max units t cp port control setup before falling edge of prog 1/15 t cy b 28 55 ns (1) t pc port control hold after falling edge of prog 1/10 t cy 125 ns (2) t pr prog to time p2 input must be valid 8/15 t cy b 16 650 ns (1) t pf input data hold time 0 150 ns (2) t dp output data setup time 2/10 t cy 250 ns (1) t pd output data hold time 1/10 t cy b 80 45 ns (2) t pp prog pulse width 6/10 t cy 750 ns notes: 1. c l e 80 pf. 2. c l e 20 pf. 3. t cy e 1.25 m s. 14
upi-41ah/42ah a.c. testing input/output waveform input/output 210393 14 a.c. testing load circuit 210393 15 driving from external source-two options l 6 mhz 210393 16 210393 17 rise and fall times should not exceed 10 ns. resis- tors to v cc are needed to ensure v ih e 3.5v if ttl circuitry is used. lc oscillator mode l c nominal f e 1 2 q 0 lc 45 h 20 pf 5.2 mhz 120 h 20 pf 3.2 mhz c e c a 3cpp 2 cpp j 510 pf pin-to-pin capacitance 210393 18 each c should be approximately 20 pf, including stray capacitance. crystal oscillator mode 210393 19 c1 5 pf (stray 5 pf) c2 (crystal a stray) 8 pf c3 20 30 pf including stray crystal series resistance should be less than 30 x at 12.5 mhz. 15
upi-41ah/42ah waveforms read operationedata bus buffer register 210393 20 write operationedata bus buffer register 210393 21 clock timing 210393 22 16
upi-41ah/42ah waveforms (continued) combination program/verify mode 210393 23 notes: 1. a 0 must be held low (0v) during program/verify modes. 2. for v ih ,v ih1 ,v il ,v il1 ,v ddh , and v ddl , please consult the d.c. characteristics table. 3. when programming the 8741ah/8742ah, a 0.1 m f capacitor is required across v dd and ground to suppress spurious voltage transients which can damage the device. verify mode 210393 29 notes: 1. prog must float if ea is low. 2. prog must float or e 5v when ea is high. 3. p 10 p 17 e 5v or must float. 4. p 24 p 27 e 5v or must float. 5. a 0 must be held low during programming/verify modes. 17
upi-41ah/42ah waveforms (continued) dma 210393 25 port 2 210393 26 port timing during external access (ea) 210393 27 on the rising edge of sync and ea is enabled, port data is valid and can be strobed. on the trailing edge of sync the program counter contents are available. 18
upi-41ah/42ah table 2. upi instruction set mnemonic description bytes cycles accumulator add a, rr add register to a 1 1 add a, @ rr add data memory 1 1 to a add a, y data add immediate to a 2 2 addc a, rr add register to a 1 1 with carry addc a, @ rr add data memory 1 1 to a with carry addc a, y data add immediate 2 2 to a with carry anl a, rr and register to a 1 1 anl, a @ rr and data memory 1 1 to a anl a, y data and immediate to a 2 2 orl a, rr or register to a 1 1 orl, a, @ rr or data memory 1 1 to a orl a, y data or immediate to a 2 2 xrl a, rr exclusive or regis- 1 1 ter to a xrl a, @ rr exclusive or data 1 1 memory to a xrl a, y data exclusive or imme- 2 2 diate to a inc a increment a 1 1 dec a decrement a 1 1 clr a clear a 1 1 cpl a complement a 1 1 da a decimal adjust a 1 1 swap a swap nibbles of a 1 1 rl a rotate a left 1 1 rlc a rotate a left through 1 1 carry rr a rotate a right 1 1 rrc a rotate a right 1 1 through carry input/output in a, pp input port to a 1 2 outl pp, a output a to port 1 2 anl pp, y data and immediate to 2 2 port orl pp, y data or immediate to 2 2 port in a, dbb input dbb to a, 1 1 clear ibf out dbb, a output a to dbb, 1 1 set obf mov sts, a a 4 a 7 to bits 4 7 of 1 1 status movd a, pp input expander 1 2 port to a movd pp, a output a to 1 2 expander port anld pp, a and a to expander 1 2 port orld pp, a or a to expander 1 2 port mnemonic description bytes cycles data moves mov a, rr move register to a 1 1 mov a, @ rr move data memory 1 1 to a mov a, y data move immediate to a 2 2 mov rr, a move a to register 1 1 mov @ rr, a move a to data 1 1 memory mov rr, y data move immediate to 2 2 register mov @ rr, move immediate to 2 2 y data data memory mov a, psw move psw to a 1 1 mov psw, a move a to psw 1 1 xch a, rr exchange a and 1 1 register xch a, @ rr exchange a and 1 1 data memory xchd a, @ rr exchange digit of a 1 1 and register movp a, @ a move to a from 1 2 current page movp3, a, @ a move to a from 1 2 page 3 timer/counter mov a, t read timer/counter 1 1 mov t, a load timer/counter 1 1 strt t start timer 1 1 strt cnt start counter 1 1 stop tcnt stop timer/counter 1 1 en tcnti enable timer/ 1 1 counter interrupt dis tcnti disable timer/ 1 1 counter interrupt control en dma enable dma hand- 1 1 shake lines en i enable ibf interrupt 1 1 dis i diable ibf inter- 1 1 rupt en flags enable master 1 1 interrupts sel rb0 select register 1 1 bank 0 sel rb1 select register 1 1 bank 1 nop no operation 1 1 registers inc rr increment register 1 1 inc @ rr increment data 1 1 memory dec rr decrement register 1 1 19
upi-41ah/42ah table 2. upi instruction set (continued) mnemonic description bytes cycles subroutine call addr jump to subroutine 2 2 ret return 1 2 retr return and restore 1 2 status flags clr c clear carry 1 1 cpl c complement carry 1 1 clr f0 clear flag 0 1 1 cpl f0 complement flag 0 1 1 clr f1 clear f1 flag 1 1 cpl f1 complement f1 flag 1 1 branch jmp addr jump unconditional 2 2 jmpp @ a jump indirect 1 2 djnz rr, addr decrement register 2 2 and jump jc addr jump on carry e 12 2 jnc addr jump on carry e 02 2 jz addr jump on a zero 2 2 jnz addr jump on a not zero 2 2 jt0 addr jump on t0 e 122 jnt0 addr jump on t0 e 022 jt1 addr jump on t1 e 122 jnt1 addr jump on t1 e 022 jf0 addr jump on f0 flag e 12 2 jf1 addr jump on f1 flag e 12 2 jtf addr jump on timer flag 2 2 e 1, clear flag jnibf addr jump on ibf flag 2 2 e 0 jobf addr jump on obf flag 2 2 e 1 jbb addr jump on accumula- 2 2 for bit intel corporation, 2200 mission college blvd., santa clara, ca 95052; tel. (408) 765-8080 intel corporation (u.k.) ltd., swindon, united kingdom; tel. (0793) 696 000 intel japan k.k., ibaraki-ken; tel. 029747-8511 printed in u.s.a./xxxx/1196/b10m/xx xx

▲Up To Search▲

Price & Availability of 8242AH

	To Download 8242AH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .